Capacitance enhancement is critical for continued scaling of trench embedded DRAM (eDRAM). In conventional trench eDRAM flow, trench capacitors are formed before CMOS logic processes. Although using high-k as the capacitor dielectric is known to enhance trench capacitance, the high thermal budget of CMOS process (e.g., STI anneal) poses constraints on the use of high-k materials that can be used in conventional trench eDRAM technology.
For example, forming a buried plate while protecting BOX is a challenge when a SOI substrate is used to manufacture eDRAM. Although the SOI substrate below the BOX can be pre-doped during SOI substrate fabrication, such an approach results in a nonconventional SOI substrate which, in turn, causes integration challenges when eDRAM and logic are formed on such a customized SOI substrate.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.